Biography:
Dr. Qing-Tai Zhao obtained his BS degree in 1987 and MS degree in 1990 both from Shandong University, and his PhD from Beijing University in 1993. Then he worked at Beijing University as a lecture and an associate professor. In 1997 he was awarded as Humboldt Fellowship and started his research at Peter Grünberg Institute 9 (PGI 9), Forschungzentrum Juelich, where he is a senior research scientist and the leader of device group in PGI 9. His primary research focuses on group IV based semiconductor devices and technology, ultra-thin silicide and Schottky barrier engineering, FDSOI and nanowire devices, high mobility transistors, energy efficient transistors, such as high power devices and tunnel-FETs. He is the author and co-author of more than 200 scientific papers, and is the holder of ~10 EU and US patents (including pending patents). He is a guest professor at Shanghai Institute of Microsystem and Information Technology, the committee member of international MAM conference.
Abstract:
Our world is becoming “Smart” due to the fast development of smart electronic devices, like smartphones, smart cars, wearable devices and internet of things (IoT). Power consumption is the biggest challenge for these devices. Therefore, energy efficient transistors are highly desired. Due to the physical limit of MOSFETs, namely the minimum slope of 60 mV/dec, the applied voltage VDD is almost in saturation at around 0.7-0.8V. To reduce the power consumption, one solution is to improve the electrostatics by using FinFET or nanowire structure to minimize the short channel effects. Another way is to use steep slope devices, like tunnel FETs (TFETs) and negative capacitance FET which can break 60mV/dec limitation. It is expected that TFET circuits will outperform subthreshold electronics at voltages around 0.2 V. However, the fabrication of well performing n- and p-type TFETs is still a great challenge. The occurrence of trap assisted tunneling (TAT) appears as one of the major obstacles to achieve steep slopes. Numerous TEFT designs, exploiting point and line tunneling as well as various materials are presently under investigation. In this presentation, I will present Si nanowire MOSFETs and TFETs. Emphasis will be placed on strained silicon n-and p-type nanowire TFETs and first complementary inverters. Gate all around TFETs with nanowire diameter down to 10nm and SiGe/Si heretostructure TFETs employing line tunneling will be presented. Negative ferroelectric capacitance FETs will be also discussed.
报告时间：2016年7月15日 下午14:30-15:30
报告地点：材料学院F220
欢迎有兴趣的师生前来参加！
深圳大学材料学院
2016年6月17日
